PCIe host controller (BCM2712 `pcie@…`) + RP1 southbridge enumeration: link training, BAR mapping at `0x1F_0000_0000`, interrupt routing for RP1 peripherals

Epic: #113 · Milestone: MC3 — Pi 5 platform drivers

Why

On the Pi 5 USB, Ethernet, GPIO, I2S, PWM and the header UARTs all live in RP1, a separate chip on a PCIe link. Nothing works in the living room without this: no USB remote, no NAS, no DAC. rpi/rp1.home (266) lists offsets but there is no PCIe host driver; drivers/pci.home is x86 config-space I/O (port 0xCF8), and pcie_extended.home is ECAM-shaped but unrun.

Tasks

• platform/bcm2712/pcie.home: bring up the internal PCIe controller from DTB (brcm,bcm2712-pcie): PHY/reset via the firmware-provided state (the bootloader already trains the RP1 link — first step is to inherit it and read config space, then own the reset sequence), ECAM config reads, BAR assignment, bus mastering, MSI/MSI-X or the legacy INTx path to the GIC (read interrupt-map from DTB).
• RP1 discovery: vendor/device ID check, map BAR1 (peripheral window), expose rp1.base + offset accessors; RP1 internal interrupt controller → per-peripheral IRQ dispatch.
• Make the existing drivers/pci.home arch-neutral (ECAM backend on ARM, 0xCF8 on x86) so NVMe/xHCI drivers share one PCI API.
• lspci shell command.

Acceptance

lspci on hardware lists RP1 (and an NVMe device when the HAT is attached); RP1 register reads return sane IDs; milestone [PCIe] RP1 at bus 1 BAR1 mapped.

Size: L · Depends on: #59, #61 · Blocks: #68, #69, #70, #72