Epic: #113 · Milestone: MC2 — Pi 5 bring-up
Why
The x86 kernel reaches 55 init milestones (PMM → VMM → buddy → slab → heap → process → signal → timer → caps → syscall → drivers → VFS → net-init → shell). All of that logic is arch-neutral Home except paging, exceptions, interrupt controller and timer, which today exist as unrun files: arch/arm64/mmu.home (184, constants only), exceptions.home, gic600.home (488), gic400.home (485, duplicated by rpi/gic400.home 683), timer.home (425).
Tasks
- MMU: identity-map RAM as normal WB cacheable, map the
0x10_0000_0000/0x1F_0000_0000peripheral windows as Device-nGnRnE, TTBR0/TTBR1 split,MAIR_EL1,TCR_EL1(T0SZ/T1SZ for 40-bit PA), enable caches; kernel higher-half mapping consistent with the x86 VMM somm/code stays shared. - Exception vectors (16 entries, 0x80 apart,
.align 11): sync/IRQ/FIQ/SError × (EL1t, EL1h, EL0 64, EL0 32); ESR/FAR decoding printed on faults;svc #0path intosys/syscall.home(x8 = syscall number, AAPCS) so the existing ring-3 tests port. - GICv3: distributor/redistributor init from DTB,
ICC_*sysregs, SPI/PPI enable, EOI; timer PPI 30 (virtual) or 26 (physical) — read from DTB. - Generic timer at 100 Hz driving the existing scheduler; monotonic clock from
CNTPCT_EL0for the perf timestamps in #49. - Delete the duplicate GIC-400 file; keep gic400 only if Pi 4 stays a target (decide in #62).
- Each subsystem prints its existing milestone string;
boot-milestones-aarch64.txtgrows to match the x86 list.
Acceptance
boot-qemu-aarch64 (virt) reaches the full milestone list through [Shell] ready with timer IRQ counter increasing; on the Pi the same list minus x86-only devices.