Epic: #113 · Milestone: MC6 — Media engine
Why
The Pi 5's only hardware video decoder is HEVC (no H.264 block). 4K content is overwhelmingly HEVC; software HEVC 4K on four A76 cores is not realistic, so this driver is what makes "4K media center" true. There is no public datasheet; the Linux stateless decoder for this block is public and documents the programming model (command FIFO per slice, the decoder does the entropy/reconstruction, the driver supplies parsed PPS/SPS/slice headers, motion-vector/collocated buffers and DPB). We implement in Home from that behavioural knowledge and the DTB (brcm,bcm2712-hevc-dec), never by copying code.
Tasks
- Spike: locate the block via DTB, map it, read ID/version, verify power/clock via mailbox; document in
docs/hardware/BCM2712_HEVC.md. - Bitstream side in Home: HEVC NAL parsing (VPS/SPS/PPS/slice headers, scaling lists) — small and arch-neutral, tested on x86 against the conformance corpus in #83; the stdlib software HEVC decoder is the reference and fallback.
- Driver: command generation per slice, coefficient/probability tables, DPB/ref-list management, output NV12 (or the block's native layout) buffers in contiguous uncached memory, interrupt-driven completion, error concealment on corrupt slices.
- Zero-copy: decoded buffers handed to the HVS video plane (#74) with a 3-deep queue; no CPU touch.
- 10-bit: Main10 path + HDR10 metadata passthrough hook.
- Gate
playback-4k-hevcon the rig: reference 4Kp60 HEVC clip, zero dropped frames over 60 s, CPU ≤ 25 %.
Acceptance
Conformance MD5 match for the HEVC Main subset via the hardware path (x86 corpus run on the rig through the shell), then the 4K gate.
Size: XL · Depends on: #74, #83, #61 (DMA-coherent memory) · Blocks: #88 (4K half)