Parent: #486 Depends on: #487, #484, #485
Goal
Lower the complete supported Wasm fixed-width and relaxed SIMD profiles to real AArch64 NEON and x86 SIMD instructions and win the published JSC SIMD matrix.
Scope
- Represent v128 values in vector registers/spills across control, calls, stack maps, traps, and deopt/fallback boundaries.
- Cover integer/float arithmetic, comparisons, conversion/narrow/widen, saturating operations, shifts, lane extract/replace, splats, shuffle/swizzle, bitselect, reductions, relaxed SIMD, and v128 memory operations.
- Select legal target instruction sequences for AArch64 and x86 feature levels with exact scalar owned fallback where hardware lacks an instruction.
- Optimize alignment, address calculation, load/store, constant/shuffle materialization, register allocation, and spill avoidance.
- Preserve exact lane semantics, NaN policies required by each corpus command, traps, bounds, endianness, and shared-memory ordering.
No-workaround rules
- No calling the portable SIMD interpreter once per instruction from “native” code, module/export recognition, relaxed substitution for strict instructions, hidden CPU requirement, or skipped rare opcode family.
Acceptance
- The complete SIMD/relaxed-SIMD opcode and corpus inventories execute through verified native attribution on each declared backend.
- Native/scalar/interpreter/JSC checksums and applicable NaN policies match for every benchmark and corpus case.
- Published integer, float, shuffle, and memory rows meet or exceed JSC at one and eight contexts, with all medians/timing floors/dispersion validated.
- Compile cost, code bytes, vector spills, runtime calls, RSS, and CPU features are recorded.
- No regression in scalar Wasm, #44 JS, GC, no-GIL, TSan, or unsupported-host fallback.
Foundation
#279–#283 and 224-sample baseline.