feat(codegen): user-space atomic intrinsics and memory ordering

Problem

Only the kernel codegen has atomics (arch_atomic_*). The user-space native backend has none — x64.zig explicitly keeps locked xchg out — and packages/intrinsics/src/atomic.zig is a Zig wrapper that Home source cannot reach.

Evidence (origin/main @ d4b219507)

• packages/codegen/src/home_kernel_codegen.zig:3335-3380
• packages/codegen/src/x64.zig:1068
• packages/intrinsics/src/atomic.zig

Scope

• Atomic<T> for integers, bools and pointers: load/store/swap/cas/fetch_add/fetch_sub/fetch_and/fetch_or.
• Orderings: relaxed, acquire, release, acq_rel, seq_cst; fences.
• Lowering on x64 (lock prefixes, mfence) and aarch64 (ldar/stlr/ldaxr/stlxr or LSE).

Acceptance criteria

• A counter incremented 1M times from 8 threads ends exactly at 8M on both architectures.
• Disassembly tests for each ordering.

Links

Related: #584, #5 Part of #814.